The present invention relates to random access memory for data storage. More specifically, the invention relates to the geometric arrangement of row and column conductors relative to memory cells in a magnetoresistive random access memory (MRAM) device.
One known MRAM memory structure uses magnetic tunnel junction memory cells and a cross-point architecture of orthogonal row and column lines. The cells are arrayed at the intersections of the orthogonal row lines and column lines. Each memory cell stores a bit of information as a function of the orientation of relative magnetization vectors in a pinned magnetic layer and a free, also called sense, magnetic layer which are separated by a non-magnetic layer. The pinned magnetic layer is so-called because its magnetization vector is fixed in a predetermined direction. The sense layer has a magnetization vector which is programmable to two different directions. The combined magnetic field patterns of the pinned and sense layers impart a resistance to the memory cell which has two different values depending on the direction of the magnetic vector in the sense layer.
The magnetic orientation of the sense layer is typically programmed to a particular magnetic orientation using magnetic fields created with the intersecting row and column lines. The row line and the column line operate in combination to switch the orientation of magnetization of the sense layer of a selected memory cell.
FIG. 1 illustrates a top view of a simplified MRAM array 1, which employs the cross-point architecture. The MRAM array includes orthogonal row lines 2, and column lines 4, and, the memory cells 6 are located at the intersections of, and between, the row and column lines. The row lines 2 and the column lines 4 are typically fabricated to have the same width as that of the memory cells 6, shown as dx for the column lines 4 and dy for the row lines 2. Although shown as rectangular in FIG. 1, the memory cells 6 can take on other shapes, for example, circular or elliptical shapes, and other shapes as well.
FIG. 2 illustrates a simplified cross section of the memory cell 6. The memory cell 6 includes a ferromagnetic sense layer 8, a ferromagnetic pinned layer 12, and a non-magnetic tunnel junction layer 10 between the sense layer 8 and the pinned layer 12. The fixed magnetic orientation of the pinned layer 12 is shown by the arrow M2. The orientation of magnetization of the sense layer 8 is not fixed and can assume two stable orientations as shown by the double headed arrow M1. The sense layer 8 can change its orientation of magnetization in response to electrical currents applied to the intersecting row and column lines (2,4) during a write operation.
The logic state of the data stored in the memory cell 6 can be determined by measuring cell resistance. When M1 and M2 are anti-parallel, e.g. a logic state xe2x80x9c0,xe2x80x9d the resistance of the memory cell 6 is the highest, whereas when M1 and M2 are parallel, e.g. logic state xe2x80x9c1xe2x80x9d the resistance is at its lowest. The resistance of the memory cell 6 is reflected by a magnitude of the current 7 passing perpendicular through the memory cell 6, as shown in FIG. 2.
In a typical MRAM array, both the row 2 and column 4 lines are used to select and write data to a memory cell 6. One of the disadvantages of the arrangement illustrated in FIGS. 1 and 2 is that the row line 2 and column line 4 take up too much space. Increased memory density requires shrinking the memory cell 6, which shrinks the corresponding dimensions of the row and column conductors.
In order to produce a required magnetic field to program the cells with row and column lines of decreased size an increased write current is required which in turn requires larger transistors. This makes it difficult to increase memory density since the larger transistors also increase chip size. Furthermore, larger write currents may also present reliability problems. The increased write current also increases power consumption and generates additional heat. This may affect the reliability of the write conductors, as the large current density may cause excessive electromigration issues.
The invention provides an MRAM memory device which has a reduced width for one or both of the orthogonal row and column lines relative to the corresponding memory cell width, and an offset of at least one of the lines relative to the cell center such that the offset conductive line overlaps an edge of a sense layer of a cell. When a memory cell is written, magnetization of the sense layer starts to reverse (nucleate) at the edge of the sense layer. With at least one of the row and column lines, being narrower than the associated cell width and offset, the magnetic direction of the sense layer of the cell can be reversed at a lower current than if the column and row lines are the same size or wider than the cell and are centered with respect to the cell.
The widths of the row and column lines and their offsets from the cell center may be identical or different.
There are other aspects and advantages of the present invention which will become more apparent from the following detailed description of the invention which is presented in conjunction with the accompanying drawings.